Within the receiver chip of the synchronous wave pipelined interface described in the U.S. patent application Ser. No. 09/263,662 entitled “Dynamic Wave Pipelined Interface Apparatus and Method Therefor”, also known as the Elastic Interface having details described in U.S. Pat. No. 6,334,163 of Dec. 25, 2001 (entitled “Elastic Interface Apparatus and Method Therefor” and used for IBM's z/900 class systems, and other similar source-synchronous pipelined (bus-pumping) chip-to-chip interfaces, data is captured using the clock signals derived from the driver chip clock, which was sent to the receiver chip as the source clock signals in separate lines and then held in the receiver storage elements (typically FIFOs) for multiple cycles.
The data in the receiver storage elements must be transferred to the receiver chip's internal logic before they are overrun by the next incoming data. It is important to determine the time of transferring data to the receiver chip's internal logic in order to minimize the system latency. The time of transferring data out the receiver storage elements usually is related to the clock cycles that data are sent by the driver chip in synchronous systems. In the previous inventions, the clock cycle to transfer data (known as target cycle) was based on the analysis of the worst-case delays. The analysis-based target cycles must be conservative for the slowest hardware in order to meet the worst-case receiver setup time. Therefore, the target cycle setting usually adds extra latency and has a danger of violating the receiver hold time thus the data in the receiver storage elements being overrun by the succeeding data.